A fault occurring anywhere in such a LSI or VLSI circuit device can have its effect propagated through a number of feedback loops including storage or memory elements in the sequential logic before reaching a testable output of the device. Level sensitive scan design (LSSD) rules were devised to eliminate the complications in testing caused by this propagation through feedback loops. As described by E. B. Eichelberger and T. W. Williams in an article entitled “A Logic Design Structure for LSI Testablility” on pages 462–468 of the Proceedings of the 14th Design Automation conf., LSSD rules impose a clocked structure on logic circuit memory elements such as latches and registers and require these memory elements be tied together to form a shift register scan path so that they are accessible for use as test input and output points. Therefore, test input signals can be introduced or test results observed wherever one of the memory elements occurs in the logic circuit. Being able to enter the logic circuit at any memory element for introducing test signals or observing test results, allows the combinational and sequential logic to be treated as much simpler combinational logic for testing purposes thus considerably simplifying test generation and analysis. Patents describing LSSD techniques include U.S. Pat. Nos. 3,783,254; 3,784,907; 3,961,252 and 4,513,418. The subject matter of these patents and the above described Eichelberger and Williams article are hereby included by reference.
As shown in FIG. 1, in accordance with LSSD rules, shift register latches (SRL's) 100 on a semiconductor chip 102 are joined together to form a shift register LSSD scan latch chain 104 to facilitate testing of combinational logic blocks 106, 108 and 110 interconnected by the SRLs 100 of the scan latch chain 104. Data is inputted to the combinational logic blocks 106, 108 and 110 and the SRLs 100 in a parallel respective primary inputs (PIs) 112 of the chip 102. Data is outputted from the combinational logic blocks 106, 108 and 110 and the SRLs 100 in parallel through the primary outputs (POs) vectors 114 of the chip 102. During testing, the scan chain latch circuits 100 may also be loaded serially. Serial input (SRI) 116 provides a serial input to the scan chain latch circuits 104. Similarly, serial output (SRO) 118 provides an output from scan chain latch circuits 104. Scanning inputs into the serial input SR 116 and out serial output 118 enables testing the SRLs 104 independently of the combinational logic 106, 108 and 110. It also allows each of the individual SRLs to be used as a pseudo-primary input or a pseudo-primary output for a combinational logic block 106, 108 or 110. The logic circuits in each of the logic blocks to be tested separately of circuits in other of the logic blocks.
A major drawback of LSSD test methodology is encountered when the LSSD scan chain circuit 104 is not functioning properly and access to the internal logic of the circuit is greatly reduced. This is often the case early in the technology or product introduction cycle when the yields are relatively low or even zero. In these situations, the rapid determination of the fault's root cause is critical, but not easily diagnosed. For example, when there is a stuck-at 0 or 1 fault on scan chain 104. For instance, with a stuck-at logic 0 fault, after a certain number of clock cycles, a serial output of logic 0's will come out of the scan chain 104 at the output 118 no matter what combination of 0's and 1's is scanned in the input 116. When this occurs, it can be determined that there is a stuck-at 0 fault in the scan chain 104, but the exact SRL 100 with the stuck-at fault condition is not isolated. While several techniques have been developed in the past to diagnose this type of failure, these techniques have produced limited success in identifying the stuck-at fault location. One series of suggestions involves modification of the structure of the latches and/or the scan chain configurations. The suggested new latch/scan chain configurations generally add hardware overhead or offer minimum or no improvement in fault coverage. In addition, scan diagnostic approaches have been proposed. Most of these test approaches are based on cause-effect algorithms. Such software solutions for diagnosing the broken scan chain generally need more storage and simulation time, and if the logic circuits between the SRLs have faults, diagnostic resolution is very poor.